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Wireless Components
2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier TUA6024 Version 2.0
Specification December 1999
Revision History: Current Version: 12.99 Previous Version:Target Data Sheet Page (in previous Version) div Page (in current Version) div Subjects (major changes since last revision)
new layout
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TUA6024
Product Info
Product Info
General Description The TUA6024 is a 5 V mixer/oscillator Package and sythesizer for analog and digital TV and VCR tuners. General
s
Features
Suitable for analog and digital terrestrial TV tuner Full ESD protection
s
Mixer/Oscillator
s
High impedance mixer input for LOW/MID band Low impedance mixer input for HIGH band 4 pin oscillator for LOW/MID band 4 pin oscillator for HIGH band IF-Amplifier balanced SAW preamplifier Low output impedance
s s s s s s
s
s s s s s
Fast I2C bus 3 NPN bandswitch buffers Internal LOW-MID/HIGH switch Lock-in flag Power-down reset Programmable reference divider ratios: 64, 80, 128 Programmable charge pump current
PLL
s s
PLL with short lock-in time High voltage VCO tuning output
s
Application
s
The IC is suitable for PAL tuner in TV- and VCR-sets or set-top receivers for analog TV and Digital Video Broadcasting.
Ordering Information
Type TUA6024-K TUA6024-S
Ordering Code Q67037-A1057 Q67037-A1056
Package P-TSSOP-28-1 P-TSSOP-28-1
Wireless Components
Product Info
Specification, December 1999
1
Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2 2.1 2.2 2.3 2.4 3 3.1 3.2 3.3 3.4 4 4.1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-4 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.4 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.1 Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.2 Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.4.3 Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-14 5.4.4 Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.4.5 Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.4.6 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Wireless Components
1-1
Specification, December 1999
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 2.4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Wireless Components
2-1
Specification, December 1999
TUA6024
Product Description
2.1 General Description
The TUA6024 device combines a digitally programmable phase locked loop (PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use in TV and VCR tuners. The PLL block with four selectable chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up to 900 MHz in increments of 31.25, 50 or 62.5 kHz. The tuning process is controlled by a microprocessor via an I2C bus. The device has three output ports. A flag is set when the loop is locked it can be read by the processor via the I2C bus. The mixer-oscillator block includes two balanced mixers (one mixer with highimpedance input and one mixer with a balanced low-impedance input), two frequency and amplitude-stable balanced oscillators for LOW/MID and HIGH, an IF amplifier, a low-noise reference voltage source, and a band switch.
2.2 Features
General
s s
Suitable for analog and digital terrestrial TV tuner Full ESD protection
Mixer/Oscillator
s s s s
High impedance mixer input for LOW/MID band Low impedance mixer input for HIGH band 4 pin oscillator for LOW/MID band 4 pin oscillator for HIGH band
IF-Amplifier
s s
balanced SAW preamplifier Low output impedance
PLL
s s s s s s s
PLL with short lock-in time High voltage VCO tuning output Fast I2C bus 3 NPN bandswitch buffers Internal LOW-MID/HIGH switch Lock-in flag Power-down reset
Wireless Components
2-2
Specification, December 1999
TUA6024
Product Description
s s
Programmable reference divider ratios: 64, 80, 128 Programmable charge pump current
2.3 Application
s
The IC is suitable for PAL tuners in TV- and VCR-sets or set-top receivers for analog TV and Digital Video Broadcasting.
2.4 Package Outlines
P-TSSOP-28-1
Wireless Components
2-3
Specification, December 1999
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Wireless Components
3-1
Specification, December 1999
TUA6024
Functional Description
3.1 Pin Configuration
OSCHIGHIN OSCHIGHOUT OSCHIGHOUT OSCHIGHIN OSCLOW/MIDIN OSCLOW/MIDOUT OSCLOW/MIDOUT OSCLOW/MIDIN RFGND ADC IFOUT IFOUT VT CP
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
HIGHIN HIGHIN LOW/MIDIN VCC MIXOUT MIXOUT PLLGND SDA SCL AS XTAL PHIGH PMID PLOW
TUA6024
22 21 20 19 18 17 16 15
Pin_config
Figure 3-1
Pin Configuration
Wireless Components
3-2
Specification, December 1999
TUA6024
Functional Description
3.2 Internal Pin Configuration
Table 3-1 Pin Definition and Function Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID 1 2 3 4 OSCHIGHIN OSCHIGHOUT OSCHIGHOUT OSCHIGHIN
1 4 2 3
HIGH 1.6 V 2.3 V 2.3 V 1.6 V
0.0 V 0.0 V 0.0 V 0.0 V
5
OSCLOW/ MIDIN
1.6 V
0.0 V
6
OSCLOW/ MIDOUT
6
7
2.8 V
0.0 V
7
OSCLOW/ MIDOUT
5
8
2.8 V
0.0 V
8
OSCLOW/ MIDIN
1.6 V
0.0 V
Wireless Components
3-3
Specification, December 1999
TUA6024
Functional Description
Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID 9 10 RFGND ADC analog ground 0.0 V VADC HIGH 0.0 V VADC
10
11
IFOUT
2.3 V
2.3 V
11
12
12
IFOUT
2.3 V
2.3 V
13
VT
VT
VT
14
14
CP
13
1.9 V
1.9 V
Wireless Components
3-4
Specification, December 1999
TUA6024
Functional Description
Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID 15 PMID
15 16 17
HIGH 5V
5 V or VCE
16
PLOW
5 V or VCE
5V
17
PHIGH
5V
VCE
18
XTAL
3.0 V
3.0 V
18
19
AS
VAS
VAS
19
20
SCL
n.a.
n.a.
20
Wireless Components
3-5
Specification, December 1999
TUA6024
Functional Description
Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID 21 SDA n.a. HIGH n.a.
21
22 23
PLLGND MIXOUT
digital ground
0.0 V 3.8 V
IF Amp.
0.0 V 3.8 V
23
24
24
MIXOUT
Oscillator
3.8 V
3.8 V
25 26
VCC LOW/MIDIN
supply voltage
5.0 V 1.8 V
5.0 V 0.0 V
26
27
HIGHIN
0.0 V
0.9 V
28
HIGHIN
27
28
0.0 V
0.9 V
Wireless Components
3-6
Specification, December 1999
TUA6024
Functional Description
3.3 Block Diagram
LOW/MIDIN
HIGHIN
HIGHIN
MIXOUT
MIXOUT
PLLGND
PHIGH
XTAL
VCC
SDA
SCL
28
27
26
25
VCC LOW or MID
24
23
22
21
20
19
AS
18
17
16
PMID
Charge Pump 13
15
I2C Bus RF Input LOW/MID
PORTS
RF Input HIGH
HIGH
FL
LOW or MID
Lock Detector Mixer LOW/MID
Crystal Oscillator
Mixer HIGH
HIGH
Reference Divider Prog. Divider
fdiv LOW or MID
Oscillator HIGH
HIGH
Oscillator LOW/MID
SAW Driver
Phase/ Frequency Comparator
ADC 1 2 3 4 5 6 7 8 9 10 11 12 14
OSCHIGHIN
OSCLOW/MIDIN
OSCHIGHIN
OSCHIGHOUT
OSCLOW/MIDOUT
ADC
IFOUT
OSCLOW/MIDIN
RFGND
IFOUT
VT
OSCHIGHOUT
OSCLOW/MIDOUT
CP
PLOW
fref
Block_diag
Figure 3-2
Block Diagram
Wireless Components
3-7
Specification, December 1999
TUA6024
Functional Description
3.4 Circuit Description
3.4.1
Mixer-Oscillator block
The mixer oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for LOW and / or MID band and HIGH, a reference voltage source and a band switch. Filters between tuner input and IC separate the TV frequency signals into two bands. The band switching in the tuner front-end is done by using two or three port outputs. In the selected band the signal passes a tuner input stage with MOSFET amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which has in case of LOW / MID a high-impedance input and in case of HIGH a low-impedance input. The input signal is mixed there with the signal from the activated on chip oscillator to the IF frequency which is filtered out at the balanced high-impedance output pair by means of a parallel tuned circuit. The following SAW preamplifier has a low output impedance to drive the SAW filter directly.
3.4.2
PLL block
The oscillator signal is internally DC-coupled as a differential signal to the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital frequency / phase detector to a reference frequency fref = 31.25, 50 or 62.5 kHz. This frequency is derived from a unbalanced, low-impedance 4 MHz crystal oscillator (pin XTAL) divided by R = 128, 80 or 64.
The phase detector has two outputs that drive two current sources of opposite palarity as charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the positive current source pulses for the duration of the phase difference. In the reverse case the I- current source pulses. If the two signals are in phase, the charge pump output (CP) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external pullup resistor at TUNE and external RC circuitry). The charge pump output is also switched into the high-impedance state if the control bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuity. TUNE may be switched off by the control bit OS to allow external adjustments.
If the VCO is not oscillating the PLL locks to a tuning voltage of 33V .
Wireless Components
3-8
Specification, December 1999
TUA6024
Functional Description
By means of control bit CP the pump current can be switched between two values by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO gains can be compensated, for example. The software-switched ports PLOW, PMID and PHIGH are general-purpose open-collector outputs. The test bit T1 = 1, switches the test signals fref (i.e.fXTAL / 64) and fdiv (divided input signal) to PLOW and PMID respectively. The lock detector resets the lock flag FL if the width of the charge pump current pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL = 1, the maximum deviation of the input frequency from the programmed frequency is given by
f = IP (KVCO / fXTAL) (C1+C2) / (C1C2)
where IP is the charge pump current, KVCO the VCO gain, fXTAL the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see Figure 4-1 Evaluation Board on page 2). As the charge pump pulses at i.e. 62.5 kHz (= fref), it takes a maximum of 16 s for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fref periods. Therefore it takes between 128 and 144 s for FL to be set after the loop regains lock.
3.4.3
I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C bus. The clock is generated by the processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the I2C bus. The data from the processor pass through an I2C bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive clock edge. The table "Bit Allocation" (see Table 5-4 Bit Allocation Read / Write on page 10) should be referred to the following description. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL.
Wireless Components
3-9
Specification, December 1999
TUA6024
Functional Description
In the data portion of the telegram during a WRITE operation, the MSB bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type has to follow the first byte. If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line is released to allow the processor to generate a stop condition. The status word consists the lock flag and the power-on flag. Four different chip addresses can be set by appropriate DC level at pin AS (see
Table 5-6 Address selection on page 11).
While applying the supply voltage, a power-on reset circuit prevents the PLL from setting the SDA line to LOW, which would block the bus. The power-on reset flag POR is set at power-on and when VCC falls below 3.2 V. It will be reset at the end of a READ operation.
Wireless Components
3 - 10
Specification, December 1999
4
Applications
Contents of this Chapter 4.1 Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Wireless Components
4-1
Specification, November 1999
TUA6024
Applications
4.1 Circuit
RGen = 75 HIGH
RGen = 75 LOW/ MID VCC
SDA
SCL
AS
PHIGH PMID
PLOW
1:1*)
4n7 68p 68p 47n
100p 220
100p 220
4n7 4 MHz 18p
4n7
4n7
4n7
22p
22p
1n L4
2p2 28 27 26 25 24 23 22 21 20 19 18 17 16 15
TUA6024
1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1 27p 22n C2 4n7
1p2
1p2
1p2
1p2
2p7
2p2
2p2
2p7
100p
L1
L2
L3
ADC 1k 100n
2:10**)
18p 82p 4k7 BB565 4k7
1p2 BA892 4n7
220 3k3 1k RLoad = 75 2k7 1n BB659C 2k7 IFoutput 100k 33k 1k
4n7 + 33 V
22k
100p
Application Circuit.wmf
Figure 4-1
Evaluation Board Table 4-1 Coils turns L1 L2 L3 L4 *) **) 1.5 3.5 8.5 14.5 E 2 mm 2.5 mm 3 mm 4 mm wire E 0.4 mm 0.5 mm 0.5 mm 0.3 mm
Table 4-1 Recommended band limits in MHz RF input min LOW MID HIGH 48.25 154.25 432.25 max 147.25 423.25 855.25 Oscillator min 87.15 193.15 471.25 max 186.15 462.25 894.25
TOKO B4F Type 617DB-1023 TOKO 7KL600 GCS-A1010DX
Wireless Components
4-2
Specification, November 1999
5
Reference
Contents of this Chapter 5.1 5.1.1 5.1.2 5.1.3 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-4 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-9 A/D converter levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 I2C Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-14 Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-14 Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Wireless Components
5-1
Specification, December 1999
TUA6024
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC may result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=--20C ... + 85C Parameter
1).
Symbol
Limit Values min max 6 +150 -40 +125 120
Unit
Remarks
Supply voltage Junction temperature Storage temperature Thermal resistance (junction to ambient) PLL CP
VCC TJ TStg RthJA
-0.3
V C C K/W
VCHGPMP ICHGPMP
-0.3
3 1 VCC
V mA V mA
Crystal oscillator pin XTAL
VXTAL IXTAL -5 -0.3
Bus input/output SDA Bus output current SDA Bus input SCL Chip address switch AS VCO tuning output (loop filter) Port outputs PLOW, PMID, PHIGH
VSDA ISDA(L) VSCL VAS VT VP IP(L)
VCC 5
V mA V V V V mA mA tmax = 0.1 sec. at 5.5 V tmax = 0.1 sec. at 5.5 V open collector
-0.3 -0.3 -0.3 -0.3 -1
VCC VCC 35 VCC 25 40
Total port output current Mixer-Oscillator Mix inputs LOW/MID Mix inputs HIGH
IP(L)
VMIX V VMIX U IMIX U
-0.3
3 2
V V mA
-5
6
Wireless Components
5-2
Specification, December 1999
TUA6024
Reference
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=--20C ... + 85C (continued) Parameter 1) Symbol Limit Values min VCO base voltage VCO collector voltage ESD-Protection all pins
2).
Unit
Remarks
max 3 VCC V V
VB VC
-0.3
VESD
1
kV
1). All values are referred to ground (pin), unless stated otherwise. Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin. 2). According to MIL STD 883D, method 3015.7 and EOS/ESD assn. standardS5.1 - 1993
Wireless Components
5-3
Specification, December 1999
TUA6024
Reference
5.1.2
Operating Range
Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed.
Table 5-2 Operating Range Parameter Symbol Limit Values min Supply voltage Programmable divider factor LOW/MID Mixer input frequency range HIGH Mixer input frequency range LOW/MID Oscillator frequency range HIGH Oscillator frequency range Ambient temperature VCC N fMIXV fMIXU fOH fOU Tamb +4.5 256 30 400 65 430 -20 max +5.5 32767 500 900 560 950 +85 MHz MHz MHz MHz C V Unit Test Conditions L Item
Wireless Components
5-4
Specification, December 1999
TUA6024
Reference
5.1.3
AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production.
Table 5-3 AC/DC Characteristics with TA 25 C, VCC Symbol min Supply Supply voltage Current consumption VCC ICC 4.5 56 5 70 5.5 84 V mA Limit Values typ max Unit Test Conditions L Item
Digital Unit
PLL Crystal oscillator connections XTAL Crystal frequency Crystal resistance Oscillation frequency Input impedance fXTAL RXTAL fXTAL ZXTAL 3.2 10 3,99975 -500 4,000 -700 4.0 4.8 100 4,00025 -900 MHz MHz series resonance series resonance fXTAL = 4 MHz fXTAL = 4 MHz
Charge pump output CP HIGH output current LOW output current Tristate current Output voltage ICPH ICPL ICPZ VCP 1.0 90 22 220 50 +1 2.5 300 75 A A nA V CP = 1, VCP = 2 V CP = 0, VCP = 2 V T0 = 1, VCP = 2 V PLL locked
Drive output VT (open collector) HIGH output current LOW output voltage I2C-Bus Bus inputs SCL, SDA HIGH input voltage LOW input voltage HIGH input current LOW input current VIH VIL IIH IIL -10 3 0 5.5 1.5 10 V V A A VIH = VS VIL = 0 V ITH VTL 10 0.4 A V VTH = 33 V, T0 = 1 ITL = 1.0 mA
Bus output SDA (open collector) HIGH output current LOW output voltage IOH VOL 10 0.4 A V VOH = 5.5 V IOL = 3 mA
Wireless Components
5-5
Specification, December 1999
TUA6024
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VCC (continued) Symbol min Edge speed SCL,SDA Rise time Fall time Clock timing SCL Frequency HIGH pulse width LOW pulse width Start condition Set-up time Hold time Stop condition Set up time Bus free Data transfer Set-up time Hold time Input hysteresis SCL, SDA Pulse width of spikes which are suppressed Capacitive load for each bus line tsudat thdat Vhys tsp CL 0 0.1 0 200 50 400 s s mV ns pF tsusto tbuf 0.6 1.3 s s tsusta thsta 0.6 0.6 s s fSCL tH tL 0 0.6 1.3 400 kHz s s tr tf 300 300 ns ns Limit Values typ max Unit Test Conditions L Item
Port outputs PLOW, PMID, PHIGH (open collector) HIGH output current LOW output voltage ADC port input HIGH input current LOW input current IADCH IADCL -10 10 A A IPOH VPOL 1 0.5 A V VPOH = 5 V IPOL = 25 mA
Address selection input AS HIGH input current LOW input current IASH IASL -50 50 A A VASH = 5 V VASL = 0 V
Wireless Components
5-6
Specification, December 1999
TUA6024
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VCC (continued) Symbol min Limit Values typ max Unit Test Conditions L Item
Analog Unit
LOW/MID Band Section (including IF amplifier) Voltage gain GV 20 23 26 dB fRF = 43.25 to 463.25 MHz, fIF = 33.4 to 58.75 MHz fRF = 43.25 to 463.25 MHz serial equivalent circuit, fMixV = 100 MHz serial equivalent circuit, fMixV = 100 MHz VCC = 5 V10% T = 25 C t = 5 s up to 15 min after switching on
Mixer noise figure Mixer input impedance
NF Ri Ci 1
9 2 2
11 3 3 400 500 100
dB k pF kHz kHz kHz
Oscillator frequency shift, PLL unlocked Oscillator frequency drift, PLL unlocked Oscillator frequency drift, PLL unlocked
fOsc(V) fOsc(T) fOsc(t)
Wireless Components
5-7
Specification, December 1999
TUA6024
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VCC (continued) Symbol min Oscillator pulling, PLL unlocked Vi 100 100 Vi N + 5 pulling, PLL unlocked N+5 -50 dBc Limit Values typ 108 108 max dBV dBV f = 10 kHz fRF = 48.25 MHz f = 10 kHz fRF = 399.25 MHz fRF = 48.25 MHz, fRF1 = 83.25 MHz, PRF=PRF1 = 80dBV fRF = 399.25 MHz, fRF1 = 439.25 MHz, PRF=PRF1 = 80dBV fm = 10kHz VMixB = 80 dBV Unit Test Conditions L Item
N+5
-50
dBc
Oscillator phase noise 1). IF suppression
OSC aIF
-80 15
-86 20
dBc/Hz dB
HIGH Band Section (including IF amplifier) Voltage gain GMixU 31 34 37 dB fRF = 367.25 MHz to 863.25 MHz, fIF = 33.4MHz to 58.75 MHz fRF = 367.25 to 615.25 MHz fRF = 623.25 to 863.25 MHz serial equivalent circuit, fMixU = 600 MHz serial equivalent circuit, fMixU = 600 MHz
Mixer noise figure
NFMixU
6 7
9 10 26 14
dB dB nH
Mixer input impedance
Ri Li
14 6
20 10
Wireless Components
5-8
Specification, December 1999
TUA6024
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VCC (continued) Symbol min Oscillator frequency shift, PLL unlocked Oscillator frequency drift, PLL unlocked Oscillator frequency drift, PLL unlocked Oscillator pulling, PLL unlocked fOsc(V) fOsc(T) fOsc(t) VMIXU 100 100 N + 5 pulling, PLL unlocked VMIXU -50 108 108 Limit Values typ max 400 800 100 kHz kHz kHz dBV dBV dBc VCC = 5 V10% T = 25 C t = 5 s up to 15 min after switching on f = 10 kHz fRF = 375.25 MHz f = 10 kHz fRF = 847.25 MHz fRF = 471.25 MHz, fRF1 = 511.25 MHz, PRF =PRF1 = 80dBV fRF = 847.25 MHz, fRF1 = 887.25 MHz, PRF=PRF1 = 80 dBV fm = 10kHz VMixB = 80 dBV Unit Test Conditions L Item
VMIXU
-50
dBc
Oscillator phase noise 1) IF suppression SAW preamplifier IF output impedance RIF LIF Rejection at the IF outputs Divider interference rejection 2) Channel S02 beat rejection 2). a a aIF
-80 15
-86 20
dBc/Hz dB
80 7
nH
serial equivalent circuit, fIF = 38.9 MHz
70 66
dBc dBc
PRF = 80 dBV fRF = 76.25 MHz PRF = 80 dBV
s This value is only guaranteed in lab.
1). Measured in evaluation board. 2). Channel S02 beat is the interfering product of fRF, fIF and fOSC of channel S02, fbeat = 37.35 MHz. The possible mechanisms are fOSC - 2 x fIF or 2 x fRFpix - fOSC. Measured in evaluation board.
Wireless Components
5-9
Specification, December 1999
TUA6024
Reference
5.2 Programming
Table 5-4 Bit Allocation Read / Write Byte Write Data Address Byte Progr. Divider Byte 1 Progr. Divider Byte 2 Control Byte Bandswitch Byte Bandswitch Byte Read Data Address Byte Status Byte 1 POR 1 FL 0 x 0 x 0 x MA1 x MA0 x 1 x A A 1 0 N7 1 x x 1 N14 N6 CP x x 0 N13 N5 T1 x x 0 N12 N4 T0 x x 0 N11 N3 FP x PHIGH MA1 N10 N2 RSA PHIGH x MA0 N9 N1 RSB PMID
1).
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
Ack
Remark s
0 N8 N0 OS PLOW
1.)
A A A A A A TUA 6024-K TUA 6024-S
PMID
1.)
PLOW
1.)
1). In a tuner PLOW and PMID are interchangeable. Both bits switch the IC into LOW/MID (VHF) mode.
Table 5-5 Description of symbols Symbol MA0, MA1 N14 to N0 CP T1, T0 FP RSA, RSB OS PLOW, PMID, PHIGH FL POR x Description Address selection bits (see Table 5-6 Address selection on page 11) programmable divider bits: N = 214 x N14 + 213 x N13 + ..... + 23 x N3 + 22 x N2 + 21 x N1 + N0 charge pump current: bit = 0: charge pump current = 50 A bit = 1: charge pump current = 220A
test bits (see Table 5-7 Test modes on page 11) reserved for future purposes, actually ignored, default: 1 reference divider bits (see Table 5-8 Reference divider ratio on page 11) tuning amplifier control bit: NPN ports control bits: PLL lock flag bit = 0: enable VT bit = 1: disable VT bit = 0: NPN open-collector output is inactive bit = 1: NPN open-collector output is active bit = 1: loop is locked
Power-on reset flag flag is set at power-on and reset at the end of READ operation don`t care
Wireless Components
5 - 10
Specification, December 1999
TUA6024
Reference
Table 5-6 Address selection Voltage at AS (0...0.1) * VCC open circuit (0.4...0.6) * VCC (0.9...1) * VCC MA1 0 0 1 1 MA0 0 1 0 1
Table 5-7 Test modes Test mode Normal operation Charge pump output, CP is in high-impedance state PLOW = fdiv output, PMID = fref output not used T1 0 0 1 1 T0 0 1 0 1
Table 5-8 Reference divider ratio Reference divider ratio 80 128 64 1). With a 4 MHz quartz. fref 1). 50 kHz 31.25 kHz 62.5 kHz RSA x 0 1 RSB 0 1 1
Table 5-9 A/D converter levels Voltage at ADC (0...0.15)*VCC (0.15...0.3)*VCC (0.3...0.45)*VCC (0.45...0.6)*VCC (0.6...1)*VCC A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0
Wireless Components
5 - 11
Specification, December 1999
Wireless Components
5.3 I2C Bus Timing Diagram
Addressing
Ack. 1st Byte
Ack.
2nd Byte Ack. 3rd Byte Ack. 4th Byte
Ack.
MA MA R/W
5 - 12 Specification, December 1999
Note: SDA:
SCL:
Telegram examples:
Abbreviations:
Start-ADB-DB1-DB2-CB-BB-Stop Start-ADB-CB-BB-DB1-DB2-Stop Start-ADB-CB-AB-DB1-DB2-Stop Start-ADB-DB1-DB2-Stop Start-ADB-CB-BB-Stop
Start= start condition ADB= address byte DB1= prog. divider byte 1 DB2= prog. divider byte 2 CB= Control byte BB= Bandswitch byte
TUA6024
Reference
Stop= stop condition
TUA6024
Reference
5.4 Test Circuits
5.4.1
Gain (GV) test Set-up in LOW/MID
50 Vmeas RMS Votmeter
LOW/ MIDIN
IFOUT
Transformer N1 V0 C V'meas N2 50 spectrum analyser
V
50
Vi
Device under Test
IFOUT
N1 : N2 = 10 : 2 turns
GVHF2
s s s s
Zi >> 50 => Vi = 2 x Vmeas = 80 dBV Vi = Vmeas + 6dB = 80 dBV V0 = V'meas + 16 dB (transformer ratio N1:N2 and transformer loss) Gv = 20 log(V0 / Vi)
5.4.2
Gain (GV) test Set-up in HIGH
HIGHIN IFOUT 50 Vmeas RMS Votmeter
Transformer N1 V0 C V'meas N2 50 spectrum analyser
V
50
Vi
Balun 1:1
Device under Test
HIGHIN IFOUT
N1 : N2 = 10 : 2 turns
GUHF2
s s s
Vi = Vmeas = 70 dBV V0 = V'meas + 16 dB (transformer ratio N1:N2 and transformer loss) Gv = 20 log(V0 / Vi) + 1 dB (1 dB = insertion loss of balun)
Wireless Components
5 - 13
Specification, December 1999
TUA6024
Reference
5.4.3
Matching circuit for optimum noise figure in LOW/MID
22p In
1n Out 7 turns wire 0.5 mm coil 5.5 mm In
15p
1n Out
22p
50 semi rigid cable 300 mm long 96 pF/m 33dB/100m
22p
NFM
For fRF = 50 MHz
s s
For fRF = 150 MHz
s s
loss = 0 dB image suppression = 16 dB
loss = 1.3 dB image suppression = 13 dB
5.4.4
Noise Figure Test Set-up in LOW/MID
Noise Source
IN
OUT
LOW/ MIDIN
IFOUT
Transformer N1 C N2
Matching Circuit
Device under Test
IFOUT
Noise Figure Meter
N1 : N2 = 10 : 2 turns NF = NFmeas - loss of matching circuit (dB)
NFVHF2
Wireless Components
5 - 14
Specification, December 1999
TUA6024
Reference
5.4.5
Noise Figure Test Set-up in HIGH
Noise Source
HIGHIN IFOUT
Transformer N1 C N2
Balun 1:1
Device under Test
HIGHIN IFOUT
Noise Figure Meter
N1 : N2 = 10 : 2 turns loss of balun = 1 dB NF = NFmeas - loss of balun (dB)
NFUHF2
5.4.6
Measurement of fref and fdiv
VVCC
+5V
Test Mode: T1 = 1, T0 = 0 5k 5k
Device under Test
PMID
fref
Counter
fQ = fref * R R: reference divider ratio
18p 4 MHz
PLOW fdiv
Counter
fVCO = fdiv * N N: divider ratio
freq_meas_cof
Wireless Components
5 - 15
Specification, December 1999

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